Design and Simulation of Synchronization Module Between Frame and Carrier in Terrestrial Digital TV

1 Introduction

China promulgated the terrestrial digital television broadcasting standard GB20600-2006 in August 2006, becoming another important national standard for terrestrial digital television broadcasting after American ATSC, European DVB-T and Japanese isdb-t. GB20600-2006 specifies the frame structure, channel coding and modulation of digital terrestrial television broadcasting (DTTB) system in China. The signal frame, the basic unit of the frame structure, adopts the cyclic extended time domain frame header structure, that is, a certain length of cyclic extended pseudo-random sequence is added in front of each 3780 symbol frame body as the frame header to provide synchronization and channel estimation for the system. This paper presents an implementation structure of receiver synchronization algorithm, which uses the known time-domain frame header to jointly carry out frame synchronization and carrier synchronization, so as to reduce the interference of carrier deviation to symbol synchronization. At the same time, the structure is implemented on FPGA to verify its feasibility and complexity.

2 Introduction to system model and basic algorithm

2.1 signal frame structure of national standard system

The data frame of the national standard system is a 4-layer structure, in which the signal frame is the basic unit of the system frame structure. As shown in Figure 1, it includes frame body and frame header. The frame body part has 3780 symbols with a duration of 500 μ s. It contains the transmitted data symbols and some system information. The frame header is m pseudo-random sequence (PN sequence), and the length depends on the frame header mode adopted by the system. The sequence of frame header is known relative to the receiver, so it can be used to realize receiver synchronization and channel estimation algorithms.

The length and content of the frame header have different provisions in different modes, but the overall structure is similar. Here, only mode 1 is exemplified to illustrate the structure of the frame header. In mode 1, the frame header length is 420 symbols, which is composed of a pre synchronization segment of 83 symbols, a pn255 sequence and a post synchronization segment of 82 symbols. The pre synchronization segment and post synchronization segment are defined as the cyclic extension of pn255 sequence.

2.2 common synchronization algorithms for time domain frame headers

2.2.1 symbol synchronization algorithm

In the system with known PN sequence as frame header, the commonly used symbol synchronization algorithm is to correlate the received signal with the local PN sequence in time domain, and then find the peak in the correlation results. The specific implementation structure is shown in Figure 2.

Because the frame header of the national standard system has a cyclic expansion structure, in the presence of multipath channel environment, the result of sliding correlation between the frame header signal and the local PN sequence is approximately the equivalent impulse response in the digital domain of the channel. Therefore, one of the multipaths can be selected as the reference path of the window opening position according to the predetermined rules. The usual approach is to give a threshold for the correlation result, and the first multipath whose correlation value exceeds the threshold is used as the reference path at the starting position of windowing. The advantage of this method is that the signals with large energy paths can be included in the windowing range to reduce inter symbol interference (ISI), and some front paths with small energy can be ignored.

2.2.2 carrier general estimation and fine estimation algorithms

In the frame header of the national standard system shown in Fig. 3, cyclic expansion is added to the front and rear ends of the PN sequence respectively. That is, the region a of the 83rd to 165th symbols of the frame header of each frame transmits the same signal as the region B of the 338th to 420 symbols. The synchronization module can use this cyclic structure to estimate the carrier frequency offset.

Assume that the received signal is

Where: l represents the symbol of frame L; N represents the nth symbol in the frame; S is the originating signal; â–³ f is the normalized carrier frequency error; N represents the number of frame body symbols of a frame; NS represents the number of symbols in a frame.

Cross correlation between segment a frame header symbol and segment B frame header symbol

Take conjugate operation. The cross-correlation result rmiddle can extract the carrier frequency error â–³ F through angle operation.

Similarly, the fine estimation part uses the frame headers of the two adjacent frames to do cross-correlation to obtain

Where: len represents the width of relevant window; Ns=4 200。

2.3 limitations of traditional symbol synchronization and carrier synchronization algorithms

The traditional symbol synchronization method mainly makes use of the good autocorrelation characteristics of PN sequence. After the local PN sequence is correlated with the frame header, a sharp correlation peak will be obtained. The frame header can be located according to the position of this correlation peak. However, when the received signal has large carrier deviation, the autocorrelation characteristics of PN sequence will be destroyed and the amplitude of correlation peak will decline. The larger the carrier deviation is, the more obvious the amplitude fading of the correlation peak is. Therefore, the larger the carrier deviation may lead to the inability of the synchronization module to accurately locate the frame head position.

In this paper, a joint structure of symbol synchronization and carrier coarse synchronization is proposed, which reduces the interference of carrier deviation to symbol synchronization, preliminarily corrects the carrier deviation, and controls the residual deviation within the range of general carrier estimation.

3 joint synchronization module architecture and FPGA implementation

3.1 hardware implementation structure block diagram

The block diagram of receiver synchronization module of national standard system proposed by the author is shown in Figure 4. The signal acquisition and synchronization process is divided into three stages:

1) Sweep symbol synchronization phase. The synchronization module scans the received data first, that is, the carrier synchronization module outputs the preset frequency to the digital oscillator (NCO) in turn and stays at each frequency point for a period of time, so that the correlation and peak detection module can find and track the frame head position. If there is no correlation peak, it can scan the next frequency point.

2) General estimation stage. When the correlation and peak detection module successfully obtains the frame synchronization information, it enters the general estimation stage. Since the frequency sweep module has preliminarily corrected the carrier deviation, the residual frequency offset is limited to the effective frequency range of the general estimation, which ensures the effectiveness of the general estimation.

3) Fine estimation stage. When the residual frequency offset is in a relatively small range, the control module will switch to fine estimation mode. The range of fine estimation is smaller than the general estimation, but the accuracy is higher than the general estimation, so it can be used to finally track the carrier frequency offset.

3.2 implementation of frequency sweep symbol synchronization module

Frequency sweep symbol synchronization is a process of scanning detection feedback. Its specific implementation structure is shown in Figure 5, which is mainly divided into three parts:

1) Detection part. It includes correlator and peak detection module. The correlator performs sliding correlation of the received signal with the local PN sequence. The peak detection module needs a preset threshold value, and compares the sliding correlation result with the threshold value. If the correlation value is greater than the threshold value, it tracks the correlation value of each point one frame away from it. If it is greater than the threshold for 3 consecutive frames, it is determined that the frame synchronization is completed and a frame synchronization signal is output. In order to realize the function of the control module at the same time, the peak detection module also outputs a peak tracking signal to the sweep control module.

2) Sweep control. Its main function is to control the scanning frequency. The frequency values of each scanned frequency point are successively stored in the ROM of the module. The control module determines whether to lock the frequency point or enter the next frequency point according to the signal output by peak detection. In order to eliminate the influence of burst interference, for each frequency point, the frequency scanning module should stay at the frequency point for a certain time, so that the correlation detection can correctly track the frame header. Due to the delay of the feedback loop, the residence time of the frequency sweep at each frequency point should be appropriately longer than the frame header detection and tracking time.

The frequency interval between adjacent frequency points of frequency sweeping shall be less than the effective frequency offset range generally estimated by the carrier, so as to ensure that the carrier estimation module can effectively estimate the residual frequency offset after frequency sweeping. The threshold of the correlation detection part should also correspond to the sweep frequency span, so that when the residual frequency offset is greater than the sweep frequency interval, the system cannot detect the correlation peak greater than the threshold.

3) Carrier deviation correction. Here, NCO is realized by accumulator, the input is the estimated frequency, and the frequency is accumulated (integrated), that is, the phase value is obtained. The output sine wave and cosine wave are realized by looking up the table.

3.3 carrier general estimation and fine estimation module

The effective estimation range of carrier general estimation for residual frequency offset is that it requires the system to determine the frame head position. Therefore, the carrier general estimation module starts to work after the synchronization of swept symbols.

The implementation block diagram of the general estimation module is shown in Fig. 6. Here, the correlation between segment a and segment B of the frame header is used to estimate the carrier frequency offset. Segment a and segment B are selected because they are located relatively behind the frame header and are not easily affected. In the case of serious ISI, because the received signal is considered as a random number with zero mean, ISI is also a random signal with zero mean. In this way, the ISI interference can be eliminated to a certain extent by averaging the long correlation window. In order to perform cross-correlation operation on the front and rear signals, the module needs a ram to store a section of frame header signal. According to the frame structure specified by the standard, the length of the cyclic suffix is 82 symbols. Therefore, RAM stores data with a length of no more than 82 symbols.

Fine estimation and general estimation are performed at the same time, but the output starts only after the general estimation tracks the carrier frequency offset for a period of time and the remaining frequency offset is less than the maximum range of fine estimation. Fine estimation cross correlates the frame headers of the two adjacent frames before and after, and the interval between the two sets of cross-correlation data is 4200 frame length. The implementation of this module can generally estimate that the segment a data of the previous frame stored in RAM is related to the segment a data of this frame. As shown in Fig. 6, when segment a data arrives, the data stored in RAM is the data of segment a of the previous frame. Therefore, the data in RAM can be read out and correlated with the received signal to complete fine estimation. The specific implementation structure is shown in Figure 7. Here, ram is read first and then written. Therefore, there is a symbol delay when data enters ram, which has no impact on the algorithm.

3.4 control sweep module

The control module is the core module of the synchronization part, and its main functions include:

1) Control the frequency sweep function. Including the output of sweep frequency and the control of sweep point transformation;

2) Control the conversion between general estimation and fine estimation. In the general estimation mode, the estimated frequency is compared with the frequency range of fine estimation. If it is found that the estimated residual frequency offset is always within the range of fine estimation (e.g. 5 consecutive frames), it is converted to fine estimation;

3) The control module also includes a low-pass filter part in the feedback loop, which performs low-pass filtering and accumulation for the estimation of carrier frequency.

4 Simulation and analysis

The baseband module is simulated on FPGA platform to verify its function. A carrier deviation of 21.17 kHz is added to the received data for simulation. The simulation environment is shown in Table 1.

Fig. 8 illustrates the simulation results, where the ordinate is the input frequency of NCO and the abscissa is the number of frames passed.

As can be seen from Fig. 8, at the initial stage of the synchronization module, the correlation module cannot find the correlation peak due to the large carrier deviation. The module tracks the carrier frequency offset through the cooperative work of frequency sweep, feedback loop, general carrier estimation and fine carrier estimation. At the same time, the frequency sweep frame synchronization also obtains the frame synchronization information. Due to the limited precision of hardware fixed-point calculation, the signal passing through the carrier synchronization module will still have a small amount of carrier frequency offset, which can be corrected by the later phase locking or equalizer module.

The synchronization module architecture proposed in this paper is realized by FPGA and simulated and synthesized with Altera QuartusII software. The occupation of resources is shown in Table 2. If the system clock of T / 2 or higher frequency is used, the correlator of frame head detection can be multiplexed by I / Q, which greatly reduces the occupation of resources. Because the algorithm is simple and the data processing speed is not high, the module has the advantages of less resources and high running frequency, which fully meets the receiving requirements of the national standard system

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