The Design of LED Large Screen Is Realized by Using Cyclone Ep1c6 and Single Chip Microcomputer SPCE

At present, the control circuit of LED large screen display system is mostly composed of single or multiple CPUs and complex peripheral circuits. This circuit design and MCU programming are complex, the debugging of the whole circuit is troublesome, and the reliability and real-time are difficult to be guaranteed. In view of this situation, this paper introduces a design scheme of LED large screen based on cyclone ep1c6. The design scheme does not need external flash ROM and ram, and does not need any external functional circuit. All functions are realized by a cyclone ep1c6 and a single chip microcomputer SPCE061A. It has the characteristics of fast data processing speed and high reliability. The application of dual port RAM in FPGA provides a new solution for data communication between different buses.

1 system structure and function overview

A design object is a block with 192 × 128 red LED dot matrix electronic screens. The whole electronic screen is a modular structure, 16 for every four × The dot matrix block of 16 is a unit, a total of 3 × Eight such units. Five screens are required to be displayed continuously on the screen, and each screen has animation effects such as moving up, down, left and right. In practical application, the distance between the main control room and the electronic screen is about 200m. Combined with the requirements of the design object and the characteristics of large screen design, the system structure block diagram is shown in Figure 1.

The LED large screen design system consists of three main units: upper computer image / text editing and sending unit, main control board unit and LED electronic screen. The upper computer of the system is controlled by a PC, which mainly edits and sends image / text information to the main control board, which processes these data and sends them to the large screen for display.

2 system hardware design

The system hardware design is mainly the design of the main control board. The main functions of the main control board include: data communication, data storage, data processing, scanning control, etc. The traditional LED large screen design is composed of flash ROM as data memory, RAM as data processing buffer, CPU and programmable logic device FPGA / CPLD, and ram as data scanning buffer. Its structure is shown in Figure 2.

The traditional hardware design of the main control board requires more peripheral devices (in some designs, there is more than one CPU and CPLD). Not only the hardware structure and wiring are complex, but also the design cost is high. In addition, due to the large amount of LED screen data, the real-time and reliable data transmission between discrete memories and before MCU and FPGA / CPLD is also a problem. In order to solve these problems, the hardware circuit of the main control board is designed with one Sunplus single chip microcomputer SPCE061A and one FPGA cycle ep1c6. The structural block diagram is shown in Figure 3.

2.1 introduction to cyclone ep1c6 and SPCE061A

Cyclone ep1c6 is a cost-effective FPGA launched by Altera, with working voltage of 3.3V and core voltage of 1.5V. Use 0.13 μ M process technology, all copper SRAM process, with a density of 5980 logic units, including 20 128 × 36 bit ram block (m4k module), with a total RAM space of 92160 bits. Two PLL circuits and a specific dual data rate interface for connecting SDRAM are embedded, and the working frequency is up to 200MHz.

2.2 structure and function of main control board

The structure of the main control board is shown in Figure 3. The data sent by the upper computer is transmitted to the RS422 receiving module [2] through twisted pair, and then sent to the single chip microcomputer after conversion. The iob7 port of the single chip microcomputer receives the data sent by the upper computer in the way of UART interrupt. The MCU writes the received serial port data in two bytes into the built-in flash one by one. The 2K word SRAM inside the single chip microcomputer is used as a buffer here. Each time the single chip microcomputer wants to write a new screen of data to the FPGA, first read the data from flash according to the specific address and store it in the SRAM, and then write the SRAM data in parallel to the dual port ram of the FPGA.

FPGA is internally configured with a dual port RAM to cache the data written by the single chip microcomputer. At the same time, these data are selectively read out from the dual port RAM according to the structure of the large screen and the characteristics of the scanning circuit. The read data is converted from parallel to series, and the large screen dot matrix is scanned and column scanned according to a certain timing. This timing is also generated by FPGA. After the scanning data and timing control signal are output from the I / O port of FPGA, they are sent to the large screen through an isolated driving circuit composed of 74ls245.

2.3 configuration of dual port RAM based on FPGA

The configuration of dual port RAM based on FPGA is the uniqueness of this design. Ram, as an intermediary, displays the data sent by the single chip microcomputer on the LED electronic screen. Because the data display is a dynamic scanning mode, if a RAM area is adopted, when the single chip microcomputer writes ram, the FPGA can only be in the waiting state. When the FPGA reads ram, the single chip microcomputer can not write data at the same time, resulting in reduced screen refresh frequency and discontinuous dynamic scanning, which affects the display effect of the screen. Therefore, two ram areas of the same size are designed: Area A and area B. When MCU writes area a, FPGA reads the data of area B. when MCU writes area B, FPGA reads the data of area A. In addition, because the FPGA scanning module can reach a high scanning rate, while the operation rate of the single chip microcomputer is relatively low, and there is a large amount of data exchange between the two modules, high-speed dual port RAM is selected to ensure that the single chip microcomputer and FPGA can read and write data at the same time on the one hand, and the data processing speed on the other hand.

CyclinE ep1c6 provides 20 storage modules with asynchronous, dual ports, register input port and optional register output port - m4k module. The storage capacity of each m4k module is 4kbit. With simple settings in quartus software, m4k module can be configured as dual port RAM, and the bit width of data and address can be selected according to actual needs. The ram designed in this paper can accommodate two screens of data. The data bit width is 16 bits and the address is 12 bits. The highest bit of the address is used as RAM partition. Each area stores one screen of data. The reading and writing of two screens are carried out at the same time. The configuration of dual port RAM is shown in Figure 4.

Figure 4 dual port RAM configuration

Wren is the write enable signal for the MCU to write data to the FPGA, wraddress [11.. 0] is the write address signal, wrclock is the write clock, data [15.. 0] is the write data, rdaddress [11.. 0] is the read address signal, rdclock is the clock signal for reading data, and Q [15.. 0] is the read data.

2.4 independent scanning unit based on FPGA

The dot matrix module is a red LED common cathode module, with 4 16 × 16 dot matrix module connected into 64 × The 16 dot matrix is controlled as a unit, and the whole large screen has 3 × Eight such units. The common interface of LEDs is used as row control, and the row scanning signal controls the on-off of multiple LEDs in a row at the same time. Based on the calculation that the current flowing through each LED is 10mA, a unit has 64 columns, and the row scanning signal must provide at least about 1A current. Therefore, before the scanning signal is sent to the LED, it must pass through a triode to improve the driving ability. The triode adopts high-speed and medium power Darlington transistor TIP127, and its collector absorbs current up to 5A to ensure line driving capacity. Since each row of the dot matrix needs a triode drive, a 64 × 16 cell blocks require 16 TIP127. The line scanning circuit is controlled by the shift register 74ls595 with latch, and each 74ls595 controls whether the 8-line dot matrix is gated or not. Because the scanning mode adopted is to scan every 8 lines of data at the same time, a 74ls595 can only light up one line of data at a time, and the lighting time of each line is the same, that is, the duty cycle is 1 / 8, so the screen brightness is very balanced.

The function of column scanning circuit is to send the column data corresponding to the row to be displayed to the cathode of LED. Column scanning is also controlled by 74ls595. The hardware structure of the screen designed in this paper is characterized by: the cathode of each 8 rows of LED is connected together, each 74ls595 controls 8 columns of data, and scans at the same time every 8 rows, for a 64 × 16 dot matrix units, a total of 8 × Two 74ls595 controls, and the 74ls595 on each line is cascaded. Each time a column scan is completed, the FPGA will output a latch signal to the 74ls595 to latch the column data, then output the row scan signal to light the corresponding row, and then latch the row scan data. In this way, the dynamic real-time display function of the whole large screen is realized in a circular manner.

Because the FPGA has performed parallel serial conversion on the data before row column scanning, the data is output serially, and is scanned at the same time every 8 lines, the whole screen row scanning only needs to occupy 1 I / O port, and the column scanning only needs to occupy 16 I / O ports, which greatly reduces the occupation of I / O. Using FPGA to design scanning logic, the key of scanning is not the hardware connection, but the configuration of chip resources.

3 software design

The software design of the system consists of three parts: the image / text editing and sending software design of upper computer, the software design of MCU control unit and the software design of FPGA control unit.

3.1 upper computer software design

The image / text editing and sending software of the upper computer is written by Visual Basic. Only set the screen size to 192 in the interface × 128. Select COM1 or com2 for the serial port, set the baud rate to 9600, set the starting address of each screen and the number of screens to be sent, call in the file containing relevant information, and click the "send" button. The software is suitable for color / monochrome screens of any size, and provides rich graphics / text editing and modification functions. It can also directly call 16 color drawing files (*. BMP) in windows.

3.2 software design of MCU control unit

The software design of MCU control unit mainly realizes three functions: serial data receiving and storage, data output and image display mode transformation. The serial data receiving part mainly receives and saves data through UART interrupt. The image display mode transformation part realizes the image transformation, such as moving up, moving down, moving left and moving right, so as to achieve rich and colorful image display effects. The single chip microcomputer software design is completed under the integrated development environment unsp ide of Lingyang technology. It is mainly composed of a C file and an ASM file. The C file includes the circular transmission and display of 5 screen data and the transformation of image display mode. The assembly file includes interrupt service subroutine and subroutine of other function calls.

3.3 FPGA control unit software design

The design of FPGA control unit is completed in QuartusII environment and described by hardware description language VHDL. Its main function is to configure dual port RAM and design scanning control circuit. The software design module of the unit is shown in Figure 5.

The configuration of dual port RAM is completely realized by setting menu in quartus environment. After configuration, a VHDL file will be automatically generated to describe the internal logic function of dual port RAM. Dual port RAM is called as a component in the whole program design.

The software design of the scanning module based on FPGA is as follows: firstly, 64 frequency division is carried out on the total clock CLK of FPGA to obtain the low level of CLK1. During this period, FPGA reads the data of dual port RAM, reads a 16 bit data every 4 CLK cycles, and reads a total of 16 numbers. During the high-level period of CLK1, FPGA performs column scanning, and outputs 16 1-bit numbers at the same time every 2 CLK cycles, a total of 32 cycles. These 16 numbers are output from parallel to series to 16 data lines. Since the speed of MCU writing ram is lower than that of FPGA processing data, the remaining 32 CLK cycles are used to wait for MCU to complete the write operation of a zone. After 12 CLK1 cycles, all the data in one row are scanned, and the FPGA outputs a column latch signal to 74ls595 to latch these data. At the same time, the row scan signal and row latch signal are output, and then the second row is scanned. Since 16 data lines are used to scan every 8 rows, the entire 128 rows of LED electronic screen only need to complete 8 Row scans, and the timing is shown in Fig. 6.